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Celoxica Agility Compiler Delivers Higher Levels of Design Abstraction; Improved C++ Support In SystemC Synthesis Tool
SAN FRANCISCO—(BUSINESS WIRE)—July 26, 2006—
Celoxica (AIM:CXA) has enhanced C++ coding support in
its Agility Compiler high level design tool, raising the level of
design abstraction above SystemC for designers who need to boost
productivity and for programmers less familiar with hardware design.
By using the C++ coding style developers can more easily exploit the
productivity gains and simulation benefits of C level design without
compromising area or timing optimization.
The Agility Compiler addresses the middle ground between the
unfulfilled promise of push-button design and the register transfer
level (RTL). Agility gives support for C++ classes, templates and
inheritance that provide powerful abstractions to shield low level
detail from the core algorithm. Communication between objects can be
done using C++ member function calls or FIFO's, and the need to use
internal SystemC ports and port mapping for object hierarchy has been
removed.
To retain the use of standard C datatypes, data width reduction
automatically trims variable widths. Agility's support for thread
processes means better ease-of-use for programmers and architects
familiar with modern processors and avoids reliance upon low-level
sc_methods.
"Customers demand a quality-of-results performance directly linked
to a level of design abstraction that delivers measurable productivity
gains, but with the necessary accuracy and control," said Jeff Jussel
vice president of marketing and general manager of the Americas for
Celoxica. "Using Agility you can dive into the low level
implementation detail, but it isn't mandatory. A simple C++ function
call can be used to turn a C array into a RAM, or you can instantiate
RAM blocks by hand and manually implement a low level RAM driver."
The Agility Compiler is a part of Celoxica's family of electronic
system level (ESL) design solutions that address the issues of
time-to-market, design complexity and high-performance computing.
Agility automatically generates RTL descriptions from high-level C/
C++/ SystemC source for popular ASIC/ SoC synthesis flows and
gate-level EDIF netlists for high density programmable logic devices.
"Our roadmap for Agility lays out the path to untimed synthesis,
but the skill of the designer remains the critical component in a
design flow and we've built Agility around them," added Jussel.
For further information about the Agility Compiler or to arrange a
demonstration contact your local Celoxica sales office or visit the
Celoxica booth, #3951 in the North Hall of the Design Automation
Conference, Moscone Center, San Francisco.
About Celoxica
A leader in electronic system level design (ESL), Celoxica is
enabling the next generation of advanced electronic products by
producing tools, boards, IP and services that turn software into
silicon. Celoxica technology raises design abstraction to the
algorithm level, accelerating productivity and lowering risk and costs
by generating semiconductor hardware directly from C-based software
descriptions. Adding to a growing installed base, Celoxica provides
the world's most widely used C-based behavioral design and synthesis
solutions to companies developing semiconductor products in markets
such as consumer electronics, defense and aerospace, automotive,
industrial and security. Celoxica is a publicly traded company on the
Alternative Investment Market of the London Stock Exchange under the
symbol CXA. For more information, visit: www.celoxica.com
Celoxica and the Celoxica logo are trademarks of Celoxica, Ltd.
All other brand names and product names are the property of their
respective owners
Contact:
Celoxica Ltd.
Jeff Jussel, 512-795-8170
Email Contact
or
VitalCom Marketing & PR
Lou Covey, 650-366-8212
Email Contact
or
Neesham PR
Peter van der Sluijs, +44-1296-628-180
Email Contact
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